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| MM74HCT273 Octal D-Type Flip-Flop with Clear February 1984 Revised May 2005 MM74HCT273 Octal D-Type Flip-Flop with Clear General Description The MM74HCT273 utilizes advanced silicon-gate CMOS technology. It has an input threshold and output drive similar to LS-TTL with the low standby power of CMOS. These positive edge-triggered flip-flops have a common clock and clear-independent Q outputs. Data on a D input, having the specified set-up and hold time, is transferred to the corresponding Q output on the positive-going transition of the clock pulse. The asynchronous clear forces all outputs LOW when it is LOW. All inputs to this device are protected from damage due to electrostatic discharge by diodes to VCC and ground. MM74HCT devices are intended to interface TTL and NMOS components to CMOS components. These parts can be used as plug-in replacements to reduce system power consumption in existing designs. Features s Typical propagation delay: 20 ns s Low quiescent current: 80 PA maximum (74HCT series) s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HCT273WM MM74HCT273SJ MM74HCT273MTC MM74HCT273N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View (c) 2005 Fairchild Semiconductor Corporation DS005760 www.fairchildsemi.com MM74HCT273 Truth Table (Each Flip-Flop) Inputs Clear L H H H H HIGH Level (steady-state) L LOW Level (steady-state) X Don't Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady-state input conditions were established. Outputs D X H L X Q L H L Q0 Clock X n n L Logic Diagram www.fairchildsemi.com 2 MM74HCT273 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per Pin (IOUT) DC VCC or GND Current, per Pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering, 10 seconds) 260qC 600 mW 500 mW Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power dissipation temperature derating--plastic "N" package: 12 mW/qC from 65qC to 85qC. 0.5V to 7.0V 1.5V to VCC 1.5V 0.5V to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC Max 5.5 VCC Units V V 4.5 0 40 85 qC DC Electrical Characteristics VCC 5V r 10% unless otherwise specified Parameter Minimum HIGH Level Input Voltage VIL VOH Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN |IOUT| |IOUT| |IOUT| VOL Minimum LOW Level Voltage VIN |IOUT| |IOUT| |IOUT| IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN VIN IOUT VIN VIH or VIL 20 PA 4.0 mA, VCC 4.8 mA, VCC VIH or VIL 20 PA 4.0 mA, VCC 4.8 mA, VCC VCC or GND, VCC or GND 0 PA 2.4V or 0.5V (Note 4) 0.6 0.8 0.9 mA 4.5V 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V V V 4.5V 5.5V VCC 4.2 5.2 VCC0.1 3.98 4.98 VCC0.1 3.84 4.84 VCC0.1 3.7 4.7 V V V 0.8 0.8 0.8 V Conditions TA Typ 2.0 25qC TA Symbol VIH 40qC to 85qC TA 55qC to 125qC Guaranteed Limits 2.0 2.0 Units V r0.1 8 r1.0 80 r1.0 160 PA PA VIH or VIL Note 4: Measured per pin, all other inputs held at VCC or GND. 3 www.fairchildsemi.com MM74HCT273 AC Electrical Characteristics VCC 5V, TA 25qC, CL 15 pF, tr tf 6 ns Conditions Typ 68 18 21 Guaranteed Limits 30 30 30 5 20 5 16 Units MHz ns ns ns ns ns ns Symbol fMAX tPHL, tPLH tPHL, tPLH tREM tS tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay from Clock to Q Maximum Propagation Delay from Clear to Q Minimum Removal Time, Clear to Clock Minimum Set-Up Time D to Clock Minimum Hold Time Clock to D Minimum Pulse Width Clock or Clear 1 6 3 10 AC Electrical Characteristics VCC 5.0V r 10%, CL 50 pF, tr tf 6 ns unless otherwise specified Conditions TA Typ 68 22 25 25qC TA Symbol Parameter 40qC to 85qC TA 55qC to 125qC Units Guaranteed Limits 21 46 44 6 25 5 25 500 19 18 56 52 7 30 5 30 500 22 MHz ns ns ns ns ns ns ns ns pF fMAX Maximum Operating Frequency 27 37 35 5 20 5 16 500 tPHL, tPLH Maximum Propagation Delay from Clock to Q tPHL, tPLH Maximum Propagation Delay from Clear to Q tREM tS tH tW tr , tf Minimum Removal Time Clear to Clock Minimum Set-Up Time D to Clock Minimum Hold Time Clock to D Minimum Pulse Width Clock or Clear Maximum Input Rise and Fall Time, Clock tTHL, tTLH Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC2 f ICC. 1 6 3 10 11 (Per Flip-Flop) 50 6 15 10 10 10 pF CPD VCC2 f ICC VCC, and the no load dynamic current consumption, www.fairchildsemi.com 4 MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HCT273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HCT273 Octal D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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